1. Field of the Invention
The present invention relates to a low power consumption programmable logic array (PLA) and a data processing system in which the PLA is incorporated.
2. Description of the Prior Art
FIG. 1 is a diagram showing the configuration of a conventional PLA which is frequently used in the prior art.
This PLA is an asynchronous type or a ratio type.
In the diagram, when a high level input signal (H or 1) is provided to an input line 10 which is one of a plurality of input lines which consist of an AND array plane of the PLA, all the array transistors, each of which comprises a N-channel conductivity type transistor, with the drain terminals connected to the input line 10, enter an ON state or an activated state.
For example, a product term line 11 connected to the power source VDD through a load transistor T11 which comprises a P channel conductivity type transistor and is in the ON state at all times is connected to ground through the array transistor T10, when the array transistor T10 enters the ON state.
In such a situation, the magnitude of the potential of the product term line 11 is determined in accordance with the rate between the ON resistance of the load transistor T11 and that of the array transistor T10. The channel conductance of the load transistor T11 is smaller than that of the array transistor T10. Accordingly, the potential of the product term line 11 is switched to a low level from a high level.
When the product term line 11 enters the low level, a plurality of array transistors in an OR array plane connected to the product term lines 11 enter the OFF state.
When the array transistor T12 enters the OFF state, the potential of an output line 12 connected to the power source VDD through a load transistor T13 comprising the P channel conductivity type transistor enters the high level from the low level.
At this time, the other array transistors connected to the output line 12 must be in the OFF state.
Therefore a low level output signal as the reversed potential of the output line 12 is provided to an output terminal OUT1 of the OR array plane.
On the other hand, when a low level input signal is provided to the input line 10 through an input terminal IN1, the operations of the AND and the OR array planes described above are reversed, the electrical potential of the product term line 11 remains at the high level, and the output signal of the high level is provided through the output terminal OUT1.
In the PLA, when the input line 10 is at the high level, the array transistor T10 is ON and a current flows continuously to ground through the transistors T10 and T11 which are in the ON state.
The array transistors other than the array transistor T10 connected to high level input line in the AND array plane are operated similarly.
When the input line is at the low level, an array transistor T12 in the OR array plane remains at the high level and the current flows continuously from the power source VDD to ground through the load transistor T13 and the array transistor T12 which are in the ON state because the product term line 11 is maintained at the high level.
The array transistors for which the gate terminals are connected to the high level product term lines are operated similarly.
Thus, a problem with the conventional PLA in the prior art is that the current flows continuously from the power source VDD to ground through the array and the load transistors when the PLA is activated.
We will explain another problem occurring when the conventional PLA described above is incorporated in a data processing system in the prior art.
FIG. 2 is a block diagram of a data processing system with the conventional PLA.
The data processing system is operated according to the following procedures:
First, instructions written in a machine language stored in the memory 70 are read out by a memory fetch unit 71, then stored in a machine language register 72. At the same time, the instruction fetch unit 72 sets a valid bit register 73a to "1".
The machine language instruction is transferred to a PLA 74, then decoded and set in the micro instruction register 75. At the same time, the content of the valid bit register 73a are set in a valid bit register 73b. An execution unit 76 implements the data processing operation in accordance with the contents of the micro instruction register 75. These units, such as the instruction fetch unit 71, the PLA 74, and the execution unit 76 described above are installed in parallel.
Thus, the steady electrical current flows continuously in the conventional PLA and the data processing system using the conventional PLA when the power source is turned on.
Namely, the electric current flows in the conventional PLA when the power source is turned on and no effective output is provided (hereinafter referred to as the unused state). The power consumption of the PLA or the data processing system in the situation described above is increased by the steady electrical current flowing therein.
The larger the scale of the PLA and the greater the number of the array transistors, the more is the power consumed when the PLA is in the unused state.
Moreover, the power consumption of the PLA is increased when it is in the unused state for a long time.
In the data processing system with the conventional PLA, no effective output of the PLA 74 can be provided when no machine language instruction is stored in the machine language register 72 and when the content of the valid bit register 73a are zero.
The power consumption of the PLA is increased because the PLA 74 is in operation when the content of the valid bit register 73a are zero.
When effective data is stored in the micro instruction register 75 (the contents of the valid bit register 73b are 1) and the execution unit 76 is executing, the contents of the micro instruction register 75 cannot be stored until the operation of the execution unit 76 is finished. Specially, even if an effective output is provided from the PLA 74, it cannot be stored in the micro instruction register 75.
Accordingly, the operation of the PLA 74 has no meaning while the valid bit register 73b is set at 1 and the execution unit 76 is executing. Thus, the power consumption of the PLA 74 is increased.